Not applicable.
Not applicable.
1. Field of the Invention
The present invention generally relates to a memory element that stores data as part of a memory cache, register file, or other memory array. More particularly, the present invention relates to a static random access memory (SRAM) element that is implemented with a plurality of ports, which can simultaneously access the memory element.
2. Background of the Invention
Memory devices store and retrieve large quantities of digital data. Memory capacities in digital systems are commonly expressed in terms of bits (binary digits), since a separate storage element is used to store each bit of data. Each storage element is referred to as a cell. Memory capacities are also sometimes quantified in terms of bytes (8 or 9 bits) or words (which may be arbitrarily defined, but commonly comprises 16 or more bits). Every bit, byte, or word is stored in a particular location, identified by a unique numeric address. Typically, one or more bytes of data is stored or retrieved during each cycle of a memory operation.
The performance of computer systems has continued to increase at a remarkable rate, while the cost has decreased just as dramatically. Part of the reason for this increased performance with decreased cost is attributable to the dramatic reduction in the cost of memory elements, while the speed and performance has increased. Current memory devices are smaller, operate at a higher speed, consume less power, and operate more reliably than the memory products that were on the market only a few years ago.
The most flexible digital memories are those that allow for data storage (or writing) as well as data retrieval (reading). Memories in which both of these functions can be rapidly and easily performed, and whose cells can be accessed in random order (independent of their physical locations), are referred to as random-access memories (RAMs). Read-only memories (ROMs) are those in which only the read operation can be performed rapidly. Entering data into a ROM is referred to as programming the ROM. This operation is much slower than the writing operation used in RAMs.
The storage cells in a typical semiconductor memory are arranged in an array consisting of horizontal rows and vertical columns. Each cell shares electrical connections with all the other cells in its row or column. The horizontal lines (which enable reading and writing operations) connect to all the cells in the row and are called word lines. The vertical lines (along which data flows into and out of the cells) are referred to as bit lines. Each cell therefore has a unique memory location, or address, which can be accessed at random through the selection of the appropriate word and bit line. Some memories are designed so that all the cells in a row are accessed simultaneously. This array configuration of semiconductor memories lends itself well to the regular structured designs that are favored in very large scale integrated circuits.
In semiconductor RAMs, information is stored in each cell either through the charging or discharging of a capacitor or the setting of the state of a bi-stable latch circuit. With either method, the information on the cell is destroyed if the power is interrupted. Such memories are therefore referred to as volatile memories. When the charge on a capacitor is used to store data in a semiconductor-RAM cell, the charge needs to be periodically refreshed, since leakage currents will remove it in a few milliseconds. Hence, volatile memories based on this storage mechanism are known as dynamic RAMs, or DRAMs. If the data is stored (written) by setting the state of a latch, it will be retained as long as power is connected to the cell (and latch is not overwritten by another write signal). RAMs fabricated with such cells are known as static RAMs, or SRAMs. Unlike DRAM cells, there is no need to refresh the cell to maintain the state of the cell.
One of the important criteria is that the memory cell does not lose its data (or change state) during a read operation. Thus, the memory cell must be stable under all normal reading conditions to ensure proper operation. At the same time, the memory cell must be writable to permit the contents of the cell to be modified when instructed by the system. In addition, the memory cell must have noise margins that are reasonable so that the memory cell holds its state even in the event that noise is present on the word lines or bit lines.
In some designs, it is desirable to have more than one read operation at a time. A dual ported memory array can support two simultaneous read operations, either from the same cell or from two cells in the same array. One cell of a conventional dual-ported SRAM array is shown in FIG. 1 for purposes of illustration. The memory array would include a plurality of memory cells constructed in much the same fashion. With a multi-ported SRAM cell, the ability to maintain the memory state of the cell during simultaneous read operations on the different ports becomes more difficult to achieve because current drawn through the access transistors increase the voltage on the xe2x80x9c0xe2x80x9d side of the latch. If not properly designed, a read operation from multiple ports could xe2x80x9cdisturbxe2x80x9d the state of the memory cell. As shown in FIG. 1, the memory cell 5 is comprised of a pair of latches (shown as inverters 10, 15) that store or hold the data. The inverters 10, 15 work in conjunction to store a data bit value. If the output of inverter 10 is a low voltage state (i.e., a xe2x80x9c0xe2x80x9d), then the output of inverter 15 will be a high voltage state (i.e., a xe2x80x9c1xe2x80x9d). Consequently, each side of the memory cell 5 is maintained at a different logical value. The state of these logical values determines whether the memory cell is storing a xe2x80x9c0xe2x80x9d or a xe2x80x9c1xe2x80x9d. For example, if the output of inverter 10 is a xe2x80x9c1xe2x80x9d, and the output of inverter 15 is a xe2x80x9c0xe2x80x9d, this may represent a xe2x80x9c1xe2x80x9d in the memory cell 5. Conversely, if the output of inverter 10 is a xe2x80x9c0xe2x80x9d, and the output of inverter 15 is a xe2x80x9c1xe2x80x9d, this may represent a xe2x80x9c0xe2x80x9d in the memory cell 5. Although only one memory cell is shown in FIG. 1, one skilled in the art will understand that multiple memory cells are configured horizontally and vertically in a two dimensional array.
Typically, a word line accesses each memory cell in a particular horizontal row. FIG. 1 shows a dual-ported SRAM cell, and thus two word lines access each memory cell in a horizontal row. In FIG. 1, these word lines are represented as wordline 1 and wordline 2. To read data from port 1, wordline 1 is asserted, thus turning on access transistors 12, 14, and thereby enabling the state of inverters 10, 15 to be read by associated port 1 bit lines. Conversely, to read data from port 2, wordline 2 is asserted, turning on access transistors 16, 18, and thereby enabling the associated port 2 bit lines to read the state of the memory cell 5.
Data is read from the memory cell 5 on two complementary bitlines, which typically are shown as extending vertically in a memory diagram. In accordance with this convention, FIG. 1 shows a low bit line and a high bit line connected to each memory cell. Thus, for example, bitline_L(1) and bitline_H(1) are used to access data in conjunction with wordline 1. When wordline 1 is asserted, the access transistor gates 12, 14 (shown as field effect transistors, or FETs) turn-on, permitting the state of inverter 10 to be read on bitline_H(1), and the state of inverter 15 to be read on bitline_L(1). If bitline_H(1) goes high, and bitline_L(1) goes low, this signals that the state of memory cell is a xe2x80x9c1xe2x80x9d (although a different convention could be used, if desired). Conversely, if bitline_H(1) goes low, and bitline_L(1) goes high, this signals that the state of memory cell is a xe2x80x9c0xe2x80x9d. The voltage levels of bitline_L(1) and bitline_H(1) are compared in a sense amp (not shown) to determine the state of the memory cell. In similar fashion, wordline 2 and access FETs 16, 18 are used to access the memory cell to have data read out on bitline_L(2) and bitline_H(2).
According to normal convention, only one word line at a time (i.e., only one port at a time) can write to the memory cell to avoid conflicts. Moreover, typically no other word line can be asserted during a write operation to prevent another port from reading from the cell during a write operation. During write operations, the appropriate bit line is pulled to ground, and the corresponding word line is asserted. This voltage differential causes a xe2x80x9c0xe2x80x9d to be written on one side of the cell.
While write operations can only be performed on one port at a time, in certain instances read operations may be performed on multiple ports simultaneously. During read operations, each bit line is charged to the power supply voltage VDD. For a multi-ported RAM cell, multiple bit lines and word lines are connected to each cell. When a read operation is performed on multiple ports, a large amount of current may be drawn into the memory cell. If the state terminal of the memory cell is at a logical xe2x80x9c0xe2x80x9d, the conduction of multiple bit lines (all of which are at VDD) will result in a current flow from the bit lines to the state terminal of the memory cell, and may potentially cause the memory cell state terminal to increase in voltage from a logical xe2x80x9c0xe2x80x9d state to a logical xe2x80x9c1xe2x80x9d state. Thus, in a situation where multiple reads occur simultaneously on multiple ports, the side of the memory cell with a xe2x80x9c0xe2x80x9d may have its voltage level raised, and thus may change the state of the latch to be a xe2x80x9c1xe2x80x9d. In some multi-ported memory arrays, there may be as many as eight ports. Such a large number of ports exaggerates the problem of disturbing the state of the memory cell during a simultaneous read operation. In particular, if eight low bit lines (bitline_L[ ]) are charged to VDD and access a memory cell simultaneously, the xe2x80x9c0xe2x80x9d state may be raised to a logic xe2x80x9c1xe2x80x9d state. Thus, the existence of an excessive number of ports in an SRAM memory array may result in corrupting the stored value in a memory cell.
To date, the solution to this problem has been to limit the number of access ports. Thus, although it may be desirable to provide a certain number of access ports, designers are forced to configure systems with fewer ports, which ultimately leads to bottlenecks in data flow, and to reduced performance of the memory system, and thus the computer system.
The present invention solves the deficiencies of the prior art by isolating the memory cell state terminals from the bit lines. In the preferred embodiment, an isolation inverter couples between the memory cell and each of the bit lines. In addition, the bit lines are selectively connected to ground to determine the state of the memory cell. This is achieved by placing a first transistor and a second transistor in the data path, with the second transistor connected at its source terminal to ground. The first transistor preferably is gated by the appropriate word line. The output of the isolation inverter preferably is used to turn on and off the second transistor. Turning on the second transistor, when the word line is enabled (which turns on the first transistor), effectively couples the associated bit line to ground, thus placing a logic xe2x80x9c0xe2x80x9d on the bit line. If the second transistor is not turned on by the inverter output when the word line is asserted causes the bit line to stay high, signaling a logic xe2x80x9c1xe2x80x9d. Thus, if the inverted output of that side of the memory cell is a xe2x80x9c1xe2x80x9d, the second transistor turns on, connecting the bit line to ground, thereby pulling the bit line low to represent a logical xe2x80x9c0xe2x80x9d. If the inverted output of the memory cell is xe2x80x9c0xe2x80x9d, the second transistor does not turn on, and the voltage on the bit line remains high, thus representing a logical xe2x80x9c1xe2x80x9d. Consequently, this configuration isolates the memory cell from the bit lines through an isolation inverter, and by using the output of the isolation inverter as a gating signal. As a result, none of the bit lines sink current in the memory cell.
According to one embodiment of the present invention, each bit line couples to a pull-down transistor stack. One of the transistors in the stack is gated by the word line associated with that port. The second transistor is gated by the state terminal of one side of the memory cell. If the word line is asserted and the state of the memory cell activates the second transistor, then the bit line is pulled to ground. If the state of the memory cell does not turn on the second transistor, then the voltage of the bit line remains high. In the preferred embodiment, the memory cell is isolated from the pull-down transistor stack by a buffer. The buffer may comprise an inverter, which inverts the state terminal of the memory cell. In the preferred embodiment, a complementary pair of bit lines is coupled to each side of the memory cell via a pull-down transistor stack.
According to another aspect of the preferred embodiment, different data paths are used to read data from, and write data to, the memory cell. The read data path comprises a path to ground that is selectively gated based on the state of the memory cell. The write data path connects through a write access transistor and a current choke (or current limiter) to the memory cell. During a write operation, the write access transistor is activated, and data can be written to the memory cell. During a read operation, the write port may remain open. The current choke preferably comprises a transistor that limits the amount of current to the state terminal of the memory cell. Thus, even though multiple bit lines may be connected to the memory cell through the write port, the current choke effectively limits the amount of current to the memory cell node while the read operation is transpiring. According to an alternative embodiment, the write port may be closed by gating the choke transistor with a write enable signal.
These and other aspects of the present invention will become apparent upon analyzing the drawings, detailed description and claims, which follow.